I am a student and have just started learning vhdl. Snake Game Html Code. So I need someone to point me in right direction. You have a component declaration COMPONENT mux41 is PORT(A,B,C,D,S0,S1:IN STD_LOGIC;Q:OUT STD_LOGIC); and an entity declaration ENTITY mux41 IS PORT( A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S: IN STD_LOGIC_VECTOR(1 DOWNTO 0); Z: OUT STD_LOGIC); END mux41; These are very different.

And the error messages tell you exactly what is wrong. Error: ELAB1_0021: try.vhd: (18, 1): Types do not match for port 'A'. Error: ELAB1_0011: try.vhd: (18, 0): Port 'S' is on entity 'mux41' but not on the component declaration. Error: ELAB1_0030: try.vhd: (18, 0): Port 'B' is on component 'mux41' but not on the entity 'mux41'. Error: ELAB1_0030: try.vhd: (18, 0): Port 'C' is on component 'mux41' but not on the entity 'mux41'.` Indeed port A is a std_logic in one, and a std_logic_vector in the other: as the message says, these do not match. And the entity has a port 'S' while the component does not. Fixing them might involve writing a new entity which matches the component, or editing the component declaration and the port maps to match the entity you already have.

And as Morten and says, catch the basic errors in simulation. If you can't get access to Modelsim, the free Xilinx tools contain a decent simulator (Isim) or there is the open-source tool GHDL. Tere Jaisa Yaar Kahan Only Beats there.

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